1. Field of the Invention
The present invention relates to an interleave control device using a nonvolatile ferroelectric memory, and more specifically, to an interleave control device configured to control interleaves of each bank individually in a signal FeRAM chip, a multi-bank FeRAM chip or a multi-bank interleave FeRAM chip, thereby reducing a row access latency.
2. Description of the Prior Art
Generally, a ferroelectric randaom access memory (hereinafter, referred to as ‘FeRAM’) has attracted considerable attention as next generation memory device because it has a data processing speed as fast as a Dynamic Random Access Memory DRAM and conserves data even after the power is turned off.
The FeRAM having structures similar to the DRAM includes the capacitors made of a ferroelectric substance, so that it utilizes the characteristic of a high residual polarization of the ferroelectric substance in which data is not low even after eliminating an electric field applied thereto.
FIG. 1 is a characteristic curve illustrating a hysteresis loop of a general ferroelectric substance.
A polarization induced by an electric field does not vanish but remains at a certain portion (‘d’ or ‘a’ state) even after the electric field is cleared due to existence of a residual (or spontaneous) polarization. The FeRAM cell is used as a memory device by corresponding the ‘d’ and ‘a’ states to binary values of ‘1’ and ‘0’, respectively.
FIG. 2 is a structural diagram illustrating a unit cell of the conventional FeRAM device.
The unit cell of the conventional FeRAM is provided with a bitline BL arranged in one direction and a wordline WL arranged in another direction vertical to the bitline BL. A plateline PL is arranged parallel to the wordline WL and spaced at a predetermined interval.
The unit cell is also provided with a transistor T1 having a gate connected to an adjacent wordline WL and a source connected to an adjacent bitline BL. A drain of the transistor T1 is connected to one terminal of a ferroelectric capacitor FC0. The other terminal of the ferroelectric capacitor FC0 is connected to the plateline PL.
The data input/output operation of the conventional FeRAM is now described referring to FIGS. 3a and 3b. 
FIG. 3a is a timing diagram illustrating a write mode of the conventional FeRAM.
At an active period, a chip enable signal CSB applied externally transits from a high to low level. If a write enable signal WEB simultaneously transits from a high to low level, the array is enabled to start a write mode. Thereafter, when an address is decoded in the write mode, a pulse applied to a corresponding wordline transits from a low to high level, thereby selecting the cell.
In the interval where the wordline WL is held at a high level, a high signal of a predetermined interval and a low signal of a predetermined signal are sequentially applied to a corresponding plateline PL. In order to write binary logic values ‘1’ or ‘0’ in the selected cell, ‘high’ or ‘low’ signals synchronized in the write enable signal are applied to a corresponding bitline BL. Here, a sense amplifier enable signal SEN is maintained at a high level.
In other words, when a high signal is applied to a bitline BL and a low signal is applied to a plateline PL, a logic value “1” is written as input data DIN in the ferroelectric capacitor FC0. When a low signal is applied to a bitline BL and a high signal is applied to a plateline PL, a logic value “0” is written as input data DIN in the ferroelectric capacitor FC0.
FIG. 3b is a timing diagram illustrating a read mode of the FeRAM.
At an active period, a chip enable signal CSB externally transits from a high to low level. All bitlines BL are equalized to a low level by an equalization signal before selection of a required wordline WL.
After each bitline BL is inactivated and an address is decoded, the required wordline WL depending on the decoded address is transited from a low to high level by the decoded address, thereby selecting a corresponding unit cell. A high signal is applied to a plateline PL of the selected cell to destroy data Qs corresponding to the logic value “1” stored in the FeRAM.
If the logic value “0” is stored in the FeRAM, its corresponding data Qns will not be destroyed. In this way, the destroyed and non-destroyed data output different values, respectively, according to the above-described hysteresis loop characteristics.
In other words, as shown in the hysteresis loop of FIG. 1, the state moves from the ‘d’ to ‘f’ when the data is destroyed while the state moves from ‘a’ to ‘f’ when the data is not destroyed. As a result, the sense amplifier is enabled by the sense amplifier enable signal SEN after the lapse of a predetermined time. When the data is destroyed, the sense amplifier outputs a logic value “1” as output data DOUT. However, when the data is not destroyed, the sense amplifier outputs a logic value “0” as output data DOUT.
After the sense amplifier amplifies the data, the data should be recovered into the original data. Accordingly, the plateline PL is inactivated from a high to low level at the state whereby a ‘high’ signal is applied to the required wordline WL.
FIG. 4 is a blcok diagram illustrating a conventional unit memory bank including a nonvolatile ferroelectric memory.
The conventional unit memory bank comprises a row selection unit 1, a column selection unit 2, a cell array block 3, a sense amplifier page buffer unit 4 and a data I/O buffer 5.
The row selection unit 1 selects a corresponding row address of inputted row addresses to output the selected row address. The cell array block 3 activates a row by a corresponding row address applied from the row selection unit 1. Data corresponding to the selected row address is outputted into the sense amplifier page buffer unit 4, and then amplified and stored therein.
The column selection unit 2 selects a corresponding column address among inputted column addresses to output the selected address into the sense amplifier page buffer unit 4. The sense amplifier page buffer unit 4 outputs data having a byte or a word width out of data stored when a corresponding column address is activated into the data I/O buffer 5. The data I/O buffer 5 buffers data from the sense amplifier page buffer unit 4.
Since a column address is a page address in the conventional unit memory bank, an extra sensing process is not required to access data. The data stored in the sense amplifier page buffer unit 4 is outputted without being sensed.
A row address further senses and amplifies data stored in a cell when data is accessed, and maintains data in a sense amplifier. Since a restore time (precharge time) is added to a row access time when data is accessed between row addresses, a longer access time is required. As a result, a row address requires a relatively longer data access time than a column address.
In the conventional unit memory bank, however, since the access time is ineffectively controlled regardless of kinds of addresses when data is accessed, the reliability of memory chips is degraded.
As a result, a device configured to perform an interleave operation using the above-described nonvolatile ferroelectric memory has been much required to reduce an unnecessary data access time and preserve stored program data even when power is off.